TC1798 Datasheet, PDF (188/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
signal is used to determine whether DQ is valid at any given clock edge. The restriction
is that the DDRCLKO signal must propagate through the TC1798 output pad in both
directions in time for the DQ and DQS signals to be latched before the next rising edge
of DDRCLKO at the clock generating flip-flop inside the EBU, i.e.
(Pad Output Delay)+(Pad Input Delay)+(Latch CK->Q valid) = t_TIME < t_ck
In addition the clock to output valid delay of the attached memory device must be less
than 0.5 * t_CK
DLL Controlled Read
The EBU interface is characterised with the DLL disabled. The relative positioning of the
DQ and DQS edges are then adjusted to determine the setup and hold times. The
parameters in the following table are therefore specified with the DLL inactive
A standard DDR device will output the DQ and DQS signals with edges that are
nominally aligned and the DLL will delay the DQS inputs internally to re-establish the
setup and hold margins.
T0
T1
T2
DDRCLKO
DDRCLKO
DQS[3:0]
DQ[31:0]
tQS
tQH
tQS
tQH
Don't Care
Data Valid
Transitioning Data
Figure 32 DLL Controlled Read
Once the DLL is enabled, to satisfy the setup time, the DQ output from the memory
device must be valid less than t_DLLR-t_QS ns after the DQS edge.
To satisfy the hold time, the DQ output from the memory device must remain valid until
the time (t_CK/2)-t_JITn-t_DLLR-t_DH before the next DQS edge.
DDRCLKO Controlled Read
A standard DDR device will output the DQ and DQS signals with edges that are
nominally aligned. In this mode, the data will be latched on both edges of the feedback
clock. This clock is generated from DDRCLKO.
Data Sheet
181
V 1.1, 2014-05