TC1798 Datasheet, PDF (183/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
Table 45 EBU DDR Timings (cont’d)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
DLL Delay time for DQS
when locked with
DLLCON.RD_ADJ=0d
t_DLLR CC t_EBU / 4 −
- 0.15
t_EBU / 4 ns
+ 0.15
DQ and DQS all signals t_DQCKH 1.0
−
−
ns
hold time after DDRCLK0 CC
edge, DDRCLK0
controlled read
DQ and DQS all signal
t_DQCKS 1.2
−
−
ns
valid to DDRCLK0 edge, CC
DDRCLK0 controlled read
DQSx edge to byte lane x t_DS1 CC −
−
1.0 ns
signals valid (DQ & DM)⁴⁾
Maximum Peak to Peak t_PKPK −
−
0
ns
jitter of the DDR clock
CC
output
DQ byte lane hold time t_QH SR 1.0 −
−
ns
after DQSx edge,
minimum hold time to
guarantee read data
capture, DLL Controlled
read
DQ byte lane valid to
t_QS SR 1.0
−
−
ns
DQSx edge minimum
setup time to guarantee
read data capture, DLL
Controlled read⁶⁾⁴⁾
1) This is a configuration constraint and not a design limit. Application code must not configure the EBU to
generate a DDR clock with a period of less than 12ns.
2) To allow for the differential clock trigger point being different from the trigger point on each of the individual
signals, this parameter will be characterised separately for each of the clock signals OCLKO, DDRCLKO and
DDRCLKO with a limit of ±1 ns
3) To allow for the differential clock trigger point being different from the trigger point on each of the individual
signals, this parameter will be characterised separately for each of the clock signals DDRCLKO (SDCLKO)
and DDRCLKO with a limit of ±2.4 ns
4) x = 0 to 3
5) i.e. signal can become invalid at most tDH1 before the clock edge
6) falling or rising edge
Data Sheet
176
V 1.1, 2014-05