TC1798 Datasheet, PDF (160/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
5.3.7 DAP Interface Timing
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Table 33 DAP Parameters
Parameter
DAP0 clock period¹⁾
DAP0 high time
DAP0 low time¹⁾
DAP0 clock rise time
DAP0 clock fall time
DAP1 setup to DAP0
rising edge
Symbol
Min.
t_TCK SR
t₁₂ SR
t₁₃ SR
t₁₄ SR
t₁₅ SR
t₁₆ SR
12.5
4
4
−
−
6.0
Values
Typ. Max.
−
−
−
−
−
−
−
2
−
2
−
−
Unit Note /
Test Condition
ns
ns
ns
ns
ns
ns
DAP1 hold after DAP0 t₁₇ SR 6.0 −
−
ns
rising edge
DAP1 valid per DAP0
t₁₉ CC 8
−
−
ns C_L= 20 pF;
clock period²⁾
f= 80 MHz
10
−
−
ns C_L= 50 pF;
f= 40 MHz
1) See the DAP chapter for clock rate restrictions in the Active:IDLE protocol state.
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t₁₁
0.5 VDDP
t_{1 5}
t_{1 2}
t_{1 3}
Figure 16 Test Clock Timing (DAP0)
Data Sheet
153
0.9 V_DDP
t₁₄
0.1 V_DDP
MC_DAP0
V 1.1, 2014-05