TC1798 Datasheet, PDF (182/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
5.3.12.5 EBU DDR Timing Parameters
Parameters applicable when using the EBU to access DDR memories
Table 45 is valid under the following conditions: C_L≤ 20 pF; V_DDEBU= 1.8 ±5% V
Table 45 EBU DDR Timings
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
DDR Clock Signal fall time t_CF CC −
−
DDR Clock Signal high t_CH CC 29
−
time
DDR Clock Signal period¹⁾ t_CK CC 24.0 −
Skew between clock rising t_CKDQS -1.2 −
transition and DQS rising CC
edge or clock falling
transition and DQS falling
edge²⁾
3.3 ns
71
%
−
ns
1.2 ns
DDR Clock Signal low
t_CL CC 47
−
time
53
%
DDR Clock Signal rise
t_CR CC −
−
3.3 ns
time
Maximum time from falling t_CVA CC −
−
5
ns
clock edge until DDR
Control signal is valid³⁾
Maximum time before
t_CVB CC −
−
5
ns
falling clock edge that
DDR control signal can
become invalid³⁾
DLL Delay time for duty
cycle correction when
locked
t_DCC CC t_EBU / 2 −
- 0.3
byte lane x signals valid t_DH1 CC -1.6⁵⁾ −
value hold time (DQ & DM)
after DQSx edge⁴⁾
t_EBU / 2 ns
+ 0.3
−
ns
DLL Delay time for for DQ t_DLL CC t_EBU / 4 −
and DM when locked with
- 0.2
DLLCON.WR_ADJ=0d
t_EBU / 4 ns
+ 0.2
Data Sheet
175
V 1.1, 2014-05