TC1798 Datasheet, PDF (157/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
5.3.5
Electrical ParametersAC Parameters
ERAY Phase Locked Loop (ERAY_PLL)
Table 31 PLL_ERAY Parameters
Parameter
Symbol
Min.
Accumulated jitter at
SYSCLK pin
D_PP CC -0.8
Accumulated_Jitter
PLL Base Frequency of
the ERAY PLL
VCO input frequency of
the ERAY PLL
D_P CC -0.5
f_{PLLBASE_} 50
ERAY ^CC
f_REF CC 20
VCO frequency range of
the ERAY PLL
PLL lock-in time
f_{VCO_ERA} 450
Y ^CC
t_L CC 5.6
Values
Typ. Max.
−
0.8
Unit Note /
Test Condition
ns
−
0.5 ns
250 360 MHz
−
40
MHz
−
500 MHz
−
200 μs
Note: The specified PLL jitter values are valid if the capacitive load per pin does not
exceed C_L = 20 pF with the maximum driver and sharp edge.
Note: The maximum peak-to-peak noise on the pad supply voltage, measured between
V_DDPF3 and V_SSPF, is limited to a peak-to-peak voltage of V_PP = 100 mV for noise
frequencies below 300 KHz and V_PP = 40 mV for noise frequencies above
300 KHz.
These conditions can be achieved by appropriate blocking of the supply voltage
as near as possible to the supply pins and using PCB supply and ground planes.
Data Sheet
150
V 1.1, 2014-05