TC1798 Datasheet, PDF (169/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
5.3.11 ERAY Interface Timing
The timings of this section are valid for the strong driver and either sharp edge or medium
edge settings of the output drivers with C_L = 25 pF.
The ERAY interface is only available for the SAK-TC1798F-512F300EP / SAK-
TC1798F-512F300EL / SAK-TC1798S-512F300EP.
Table 38 ERAY Parameters
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
Time span from last BSS
to FES without the
influence of quartz
tolerancies (d10Bit_TX)¹⁾
t₆₀ CC
997.75 −
1002.2 ns
5
TxD data valid from
t₆₁-t₆₂ −
−
1.5 ns Asymmetrical
fsample flip flop txd_reg CC
delay of rising
TxDA, TxDB
and falling edge
(dTxAsym)²⁾³⁾
(TxDA, TxDB)
Time span between last t₆₃ SR 966 −
BSS and FES without
influence of quartz
tolerancies
(d10Bit_RX)¹⁾⁴⁾⁵⁾
1046.1 ns
RxD capture by fsample t₆₄-t₆₅ −
−
3.0 ns Asymmetrical
(RxDA/RxDB sampling CC
delay of rising
flip-flop) (dRxAsym)⁶⁾
and falling edge
(RxDA, RxDB)
TxD data delay from
dTxdly −
−
10.0 ns Px_PDR.PDy =
sampling flip-flop
CC
000_B
−
−
15.0 ns Px_PDR.PDy =
001_B
RxD capture delay by
dRxdly −
−
10.0 ns
sampling flip-flop
CC
1) This includes the PLL_ERAY accumulated jitter.
2) Refers to delays caused by the asymmetries of the output drivers of the digital logic and the GPIO pad drivers.
Quarz tolerance and PLL_ERAY accumulated jitter are not included.
3) E-Ray TxD output drivers have an asymmetry of rising and falling edges of |t_FA2 - t_RA2| ≤ 1 ns.
4) Limits of 966ns and 1046.1ns correspond to (30%, 70%) * V_DDP FlexRay standard input thresholds. For input
thresholds of this product, a correction of - 0.5 ns and +0.1 ns has to be applied.
Data Sheet
162
V 1.1, 2014-05