TC1798 Datasheet, PDF (12/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Summary of Features
– 128 Kbyte Memory (SRAM)
– 16 Kbyte BootROM (BROM)
• 16-Channel DMA Controller
• 8-Channel Safe DMA (SDMA) Controller
• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels
serviced by CPU or PCP2
• High performing on-chip bus structure
– 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– One bus bridge (SFI Bridge)
• Versatile On-chip Peripheral Units
– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
– Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
– Four SSC Guardian (SSCG) modules, one for each SSC
– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
– One External Bus Interface (EBU) supporting different memories: asynchronous
memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR
flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0
(limited frequency at 1.8 V I/O supply)
– One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
– One FlexRay^TM module with 2 channels (E-Ray).
– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
– Two Capture / Compare 6 modules
– Two General Purpose 12 Timer Units (GPT120 and GPT121)
• 64 analog input lines for ADC
– 4 independent kernels (ADC0, ADC1, ADC2, and ADC3)
– Analog supply voltage range from 3.3 V to 5 V (single supply)
• 4 different FADC input channels
– channels with impedance control and overlaid with ADC1 inputs
– Extreme fast conversion, 21 cycles of f_FADC clock
– 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• 8 digital input lines for SENT
– communication according to the SENT specification J2716 FEB2008
Data Sheet
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V 1.1, 2014-05