TC1798 Datasheet, PDF (185/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
T0
DDRCLKO
DDRCLKO
CKE
Command
ADDR
T1
T2
t_CVA
t_CVA
t_CVB
t_CVA
t_CVB
VALID
t_CVA
t_CVB
VALID
NOP
Don't Care
Figure 30 DDR command and Address Timing
Using the DDRNCON.AMODE field, the timing of the address can be changed so that
the address changes on the rising clock edge and is held for two clock cycles. This allows
a nominal setup and hold margin of a full clock cycle. This mode is not compatible with
burst length of two as commands needing a valid address output can then be generated
in consecutive clock cycles.
Timing of DDR Write Data
The EBU will generate the DQ (write data) DM and DQS signals in two different modes
depending on the ratio of the internal to external clocks.
If the ratio is 1:1, then the clock used to generate the DQ and DM outputs must be shifted
by the DLL by 25% of the external clock period (nominal value).
If the ratio is 1:2 or 1:4, then the DQ and DM signals will be generated using edges of
the internal clock and the DLL must not be used to further adjust the edge timing.
A ratio of 1:3 is not supported.
In all cases, the edges of the DQS signals are nominally aligned to the clock output and
the DQS waveform is in phase with, and the same frequency as, the memory device
clock input.
Data Sheet
178
V 1.1, 2014-05