TC1798 Datasheet, PDF (179/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
Table 43 EBU Burst Read Timings (cont’d)
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
WAIT setup (low or high) t₂₅ SR 3
−
−
ns
to BFCLKI rising edge ¹⁾
WAIT hold (low or high) t₂₆ SR 0
−
−
ns
from BFCLKI rising edge¹⁾
1) Not subject to production test, verified by design/characterization.
2) An active edge can be rising or falling edge, depending on the settings of bits BFCON.EBSE / ECSE and clock
divider ratio. Negative minimum values for these parameters mean that the last data read during a burst may
be corrupted. However, with clock feedback enabled, this value is oversampling not required for the LMB
transaction and will be discarded. If the clock feedback is not enabled, the input signals are latched using the
internal clock in the same way as at asynchronous access. So t14, t15, t16, t17, t18 and t19 from the
asynchronous timings apply.
3) For BUSCONx.EBSE=1B and BUSAPx.EXLCLK=00B, ADV will change normally on the clock edge so this
parameter is used directly.
For BUSCONx.EBSE=1B and other values of BUSAPx.EXTCLK, ADV and BAA add the high pulse width of
EBUCLK to this parameter.
For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=00B add the high pulse width of EBUCLK to this parameter.
For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=11B add two EBUCLK periodsto this parameter to get the
hold time from BFCLKO rising edge to the ADV.
For BUSCONx.EBSE=0B and BUSAPx.EXTCLK=01B or 10B add 1 EBUCLK period.
Please note that the high pulse width of EBUCLK is defined by the high pulse width of fVCO of the used PLL.
Data Sheet
172
V 1.1, 2014-05