TC1798 Datasheet, PDF (184/200 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1798
Electrical ParametersAC Parameters
Timing for EBU DDR Clock Outputs
The EBU provides three possible DDR clock outputs depending on the type of device
being accessed. These are
• Differential clock for accessing devices using a DDRAM type protocol on the
DDRCLKO and DDRCLKO pins.
• Differential clock for accessing devices using a burst flash type protocol on the
BFCLKO and DDRCLKO pins.
• A single-ended clock on OCLKO (MR/W) for interfacing to ONFI 2 compliant devices.
All these clocks operate with identical timing parameters and have a restricted load limit
of 10pF for DDR operation.
The rising edge on the differential clocks is defined as when a rising edge on DDRCLKO
or BFCLKO transitions past a falling edge on DDRCLKO.
Timings apply at VDD_EBU = 1.8 volts
t_CK
0.5 VDD_EBU
t_CH
t_CL
t_CF
0.9 VDD_EBU
t_CR ^{0.1 VDDEBU}
Figure 29 Timing Waveform for DDR Clock Signals
Timing for EBU DDR Control Outputs
The EBU control state machine will ensure that commands and signal transitions are
generated in the correct clock cycle to meet device requirements. This section also
applies when accessing SDRAM devices.
The EBU will generate address (A[15:0]) and control (CKE, RAS, CAS, WR) outputs on
the falling edge of the DDR clock to allow nominally symmetric setup and hold margins
around the rising edge of the clock. For SDRAM devices, the same address and control
signals are required but, in addition, the write data (AD[31:0]) and DQM signals (BC[3:0])
are required to meet the same timing requirements.
As these parameters apply to SDRAM as well as DDR devices, the load limit should be
taken to be 40pF.
Data Sheet
177
V 1.1, 2014-05