IC-TW28 Datasheet, PDF (75/80 Pages) IC-Haus GmbH – 10-BIT SIN/COS INTERPOLATOR

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Rev D2, Page 75/80
BUSSING MULTIPLE iC-TW28s
Multiple iC-TW28 slaves can be used with a single SPI gether and each device uses a separate Slave Select
host in a traditional SPI bus connection. In this case, (xSS) signal, as shown below.
SCLK, SI, and SO on all devices are connected to-
Host µP
iC-TW28 3
xSS
SCLK
SI
SO
xIRQ
iC-TW28 2
xSS
SCLK
SI
SO
xIRQ
iC-TW28 1
xSS
SCLK
SI
SO
xIRQ
xCS3
xCS2
xCS1
SCLK
MO
MI
xIRQ1
xIRQ2
xIRQ3
Figure 45: SPI Bus Connection of Multiple iC-TW28s
In operation, the host initiates communication with one
of the iC-TW28s by activating the appropriate chip se-
lect (xCS) and then clocking a 32-bit SPI command to
the Slave Input, SI, while at the same time reading the
32-bit response to the previous command on the Slave
Output, SO. This behavior is the same as with a single
iC-TW28. Note that with a bussed connection, the host
communicates with only one iC-TW28 slave at a time.
As shown, the interrupt request outputs (xIRQ pins)
of the bussed iC-TW28s are connected to their
own interrupt request input on the host processor.
It is recommended to use push-pull xIRQ outputs
(MAIN_CFG.irqpp = 1) with bussed iC- TW28s.
iC-TW28 3
xSS
SCLK
SO
SI
xIRQ
iC-TW28 2
xSS
SCLK
SO
SI
xIRQ
iC-TW28 1
xSS
SCLK
SO
SI
xIRQ
3.3V
Host µP
xCS
SCLK
MO
xIRQ
MI