IC-TW28 Datasheet, PDF (31/80 Pages) IC-Haus GmbH – 10-BIT SIN/COS INTERPOLATOR

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Rev D2, Page 31/80
The type of data written by an SPI read/write command
is determined by the write mode encoded in the control
byte of the command packet as shown below.
SPI Write Modes
wm
Description
0
Null Write (read only)
1
Multi-Cycle Counter Write
2
Multi-Cycle Counter Atomic Read/Write
3
Register Write
Table 15: SPI Write Modes
The type of data returned by an SPI read-only or read-
/write command is determined by the read mode en-
coded in the control byte of the command packet as
shown below.
tion Read), the command bits in the command packet
are used to specify the register address to read. See
Register Data and Position Read on page 32 for more
information.
Multi-Cycle Counter Write
The Multi-Cycle Counter Write command packet is for-
matted as shown below.
Bits
31:24
23:15
14:1
0
Multi-Cycle Counter Write: wm = 1
Description
SPI Control Byte
Reserved (must be 0)
Multi-Cycle Counter Value (0 – 16,383)
Multi-Cycle Counter Synchronization Bit (mcs)
Table 18: Multi-Cycle Counter Write Command Packet
SPI Read Modes
rm
Description
0
Position and Status Read (20 ns or 320 ns)
1
Captured Position and Status Read
2
Sin, Cos, and Zero ADC Read (320 ns)
3
Register Data and Position Read
Table 16: SPI Read Modes
The requested values are returned in the subsequent
response packet. Position (angle) is always returned at
the full 10-bit resolution of the iC-TW28, regardless of
the interpolation value (INTER).
All values are read on the falling edge of xSS. How-
ever, the internal update rates of the various values
are different. In all cases, the value read is the most
recently updated internal value. See Response Packet
Formats on page 32 for more details on the internal
update rates.
Null Write (Read Only)
The Null Write command packet is formatted as shown
below.
The specified multi-cycle counter value is written imme-
diately to the multi-cycle counter and the data specified
by the read mode in the control byte is returned with
the next SPI command.
The multi-cycle counter synchronization bit (mcs) allows
synchronization between an external absolute system
and the multi-cycle counter in the iC-TW28, even when
the sin/cos inputs are moving. See Multi-Cycle Counter
on page 67 for more information.
Multi-Cycle Counter Atomic Read/Write
The Multi-Cycle Counter Atomic Read/Write command
packet is formatted as shown below.
Multi-Cycle Counter Atomic Read/Write: wm = 2
Bits
Description
31:24
SPI Control Byte
23:15
Reserved (must be 0)
14:1
Multi-Cycle Counter Value (0 – 16,383)
0
Multi-Cycle Counter Synchronization Bit (mcs)
Table 19: Multi-Cycle Counter Atomic Read/Write Com-
mand Packet
Bits
31:24
23:0
Null Write: wm = 0
Description
SPI Control Byte
Ignored (Register Address if rm = 3)
Table 17: Null Write Command Packet
The Null Write (Read Only) command does not write
any data to the iC-TW28. The data specified by the
read mode in the control byte is returned with the next
SPI command.
The Multi-Cycle Counter Atomic Read/Write command
is like the Multi-Cycle Counter Write command except
that the specified multi-cycle counter value is written to
the multi-cycle counter at the same instant as the data
specified by the read mode in the control byte is read.
Writing of the multi-cycle counter value is delayed until
the next SPI command to allow simultaneous reading of
the position and writing of the multi-cycle counter value
for synchronization confirmation when using external
absolute systems. See Multi-Cycle Counter on page 67
for more information.
If rm = 0, 1, or 2, the command bits in the command
packet are ignored, but must be present to complete
the 32-bit packet. If rm = 3 (Register Data and Posi-