IC-TW28 Datasheet, PDF (32/80 Pages) IC-Haus GmbH – 10-BIT SIN/COS INTERPOLATOR

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Rev D2, Page 32/80
Register Write
The Register Write command packet is formatted as
shown below.
The SPI Status Byte reports the status of the signal path,
the most recent capture, and the multi-cycle counter as
shown below.
Bits
31:24
23:8
7:0
Register Write: wm = 3
Description
SPI Control Byte
Register Address
Register Data
Table 20: Register Write Command Packet
The specified register data is written to the register at
the specified register address and the data specified by
the read mode in the control byte is returned with the
next SPI command.
Response
Bit
Bit
31:30
7:6
29
5
28
4
27
3
26
2
25
1
24
0
SPI Status Byte
Name Description
–
0 (Reserved)
fflt
Fatal Fault Occurred
irq
Interrupt Request Active
zcl
Zero Capture Lost
zc
Zero Capture Occurred
mcrl
Multi-Cycle Counter
Rollover Lost
mcr
Multi-Cycle Counter
Rollover Occurred
Table 23: SPI Status Byte
Register Data and Position Read
The Register Data and Position Read command packet
is formatted as shown below.
Register Data and Position Read: rm = 3, wm = 0
Bits
Description
31:24
SPI Control Byte
23:8
Register Address
7:0
Ignored
Table 21: Register Data and Position Read Command
Packet
The data at the specified register address as well as
the multi-cycle counter and angle values are returned
with the next SPI command.
Note that the Register Data and Position Read Com-
mand requires the write mode in the SPI Control Byte
(wm) to be zero. Non-zero wm values result in unde-
fined operation.
The Fatal Fault (fflt) bit is set if one or more of the bits
in the STAT_FATAL register is set, indicating that a fatal
fault occurred. The interpolator is disabled after a fatal
fault and must be restarted by a serial command or by
cycling power.
The Interrupt Request (irq) bit indicates that there is a
pending internal interrupt request or fault.
The Zero Capture Occurred (zc) bit is set whenever a
zero capture event occurs. This bit is reset when the
captured position is read. A zero capture event can
also be configured to request an interrupt to the host
processor by asserting xIRQ. See STAT_CFG on page
46 for more information.
The Zero Capture Lost (zcl) bit is set whenever a zero
capture event occurs while the Zero Capture Event (zc)
bit is still active. This condition indicates that the cap-
tured position from a previous capture event has been
lost. This bit is reset when the captured position is read.
See Position Capture on page 69 for more information.
Response Packet Formats
The format of the response packet is determined by the
read mode specified in the control byte of the previous
command packet.
Position and Status Read
The Position and Status Read response packet is for-
matted as shown below.
Bits
31:24
23:10
9:0
Position and Status Read Response: rm = 0
Description
SPI Status Byte
Multi-Cycle Counter Value (0 – 16,383)
Angle Value (0 – 1023)
Table 22: Position and Status Read Response Packet
The Multi-Cycle Counter Rollover Occurred (mcr) bit is
set whenever the multi-cycle counter passes through
a multiple of 4,096 cycles. This bit is reset whenever
the position is read. A multi-cycle counter rollover can
also be configured to request an interrupt to the host
processor by asserting xIRQ. See STAT_CFG on page
46 for more information.
The Multi-Cycle Counter Rollover Lost (mcrl) bit is set
whenever the multi-cycle counter passes through a
multiple of 4,096 cycles while the Multi-Cycle Counter
Rollover (mcr) bit is still active. This condition indicates
that a previous multi-cycle counter rollover was not ac-
knowledged. This bit is reset whenever the position is
read. See Multi-Cycle Counter on page 67 for more
information.