IC-TW28 Datasheet, PDF (67/80 Pages) IC-Haus GmbH – 10-BIT SIN/COS INTERPOLATOR

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Rev D2, Page 67/80
MULTI-CYCLE COUNTER
The iC-TW28’s 14-bit multi-cycle counter continuously
tracks up to 16,383 input cycles during operation. In
serial configuration mode, the multi-cycle counter can
be read and written via the SPI port and can be config-
ured to reset on the rising edge of the Z output. The
multi-cycle counter cannot be read using the Encoder
Link interface.
To use the multi-cycle counter, select whether or not the
multi-cycle counter is to be reset whenever the Z output
is activated using ZERO0.clr. If ZERO0.clr = 0, the mul-
ti-cycle counter is never cleared. If ZERO0.clr = 1, the
multi-cycle counter is cleared (set to zero) whenever
the Z outputs are activated. Clearing the counter on
the Z output is useful to ensure that multi-cycle counter
never rolls over and is always in sync with the external
system.
The multi-cycle counter value is a 14-bit number repre-
senting the number of input cycles seen by the iC-TW28
since it was started or restarted or since the multi-cy-
cle counter was reset. The multi-cycle counter value
and the 10-bit interpolated angle within an input cycle
are always read together as a 24-bit position value.
See Response Packet Formats on page 32 for more
information.
The multi-cycle counter can be preset by writing a
value to it. This is useful to synchronize the multi-cycle
counter with an external absolute system, for exam-
ple. Write the new value for the multi-cycle counter
and the multi-cycle counter synchronization bit using
the multi-cycle counter write command via the SPI port.
See Multi-Cycle Counter Write on page 31 for more
information.
The multi-cycle counter synchronization bit is used to
ensure proper updating of the multi-cycle counter when
the sin/cos inputs are moving or if the external absolute
system in misaligned. It indicates in which sector (half
period) of an input cycle the sensor angle is expected
to be when the multi-turn position is updated. This al-
lows correcting the new multi-turn counter value if the
external absolute system in misaligned by up to ±90^◦
of an input cycle or if the sin/cos inputs move during
the presetting of the multi-cycle counter.
Value
0
1
Multi-Cycle Counter Synchronization Bit: mcs
Description
0^◦(0) ≤ Sensor Angle < 180^◦ (511)
180^◦(0) ≤ Sensor Angle < 360^◦ (1023)
Table 124: Multi-Cycle Counter Synchronization Bit
The multi-cycle counter rollover occurred (mcr) bit in
the SPI status byte is set whenever the multi-cycle
counter passes through a multiple of 4,096 cycles. For
example, with continuous positive rotation, the mcr bit
is set when the counter passes through values of 4,096,
8,192, 12,288, and 0. Hysteresis of 4,096 cycles is
employed to avoid setting the mcr bit multiple times
due to direction reversals. For example, after the mcr
bit is set at 4,096 cycles with positive rotation, if the
direction of rotation reverses, mcr will not be set again
passing through 4,096, but will be set again when pass-
ing through 0. The multi-cycle counter rollover occurred
bit is reset whenever the position is read.
If the sin/cos input sector indicated by the multi-cycle
counter synchronization bit matches the actual sin/cos
input sector, the multi-turn counter is preset to the value
in the command. If not, the multi-turn counter is preset
to the value in the command ±1 because the input has
moved to the next (or previous) cycle.
Specifically, if mcs = 0 and 270^◦ (768) ≤ Sensor Angle
< 360^◦ (1023), the multi-cycle counter is preset to the
value in the command – 1. If mcs = 1 and 0^◦ (0) ≤
Sensor Angle ≤ 90^◦ (256), the multi-cycle counter is
preset to the value in the command + 1. Otherwise,
the multi-cycle counter is preset with the value in the
command, as shown in Figure 38.
If multiple rollovers occur before the position is read, the
multi-cycle counter rollover lost (mcrl) bit is set. This
indicates that a previous multi-cycle counter rollover
was not acknowledged. This bit is reset whenever the
position is read.
The host microprocessor or microcontroller can poll the
multi-cycle counter rollover occurred (mcr) bit in the SPI
status byte to determine when a counter rollover has
occurred. A multi-cycle counter rollover can also be
configured to interrupt the host processor by asserting
xIRQ. See STAT_CFG on page 46 for more information.
180°
90°
0
–1
0° 180°
90°
+1
0°
0
270°
270°
mcs = 0
mcs = 1
Figure 38: Multi-Cycle Counter Synchronization