IC-TW28 Datasheet, PDF (68/80 Pages) IC-Haus GmbH – 10-BIT SIN/COS INTERPOLATOR

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Rev D2, Page 68/80
For example, if the sensor angle is between 0^◦ and
180^◦ when the multi-cycle counter write command is
initiated, then mcs is set to 0 in the command. When
the command is executed by the iC-TW28 and the mul-
ti-cycle counter is preset, if the sensor angle is between
0^◦ and 270^◦, it must have moved clockwise across 0^◦
and into the previous input cycle. Thus, the multi-cycle
counter is preset to one cycle less than the commanded
value (-1).
Therefore, it is necessary to know the sensor angle
sector (half-period) prior to executing the multi-cycle
counter write command. In the absence of an exter-
nal absolute system, the sin/cos input sector can be
determined by the MSB of the 10-bit sensor angle. An
external absolute system must supply its own sector
information.
The complete sequence for presetting the multi-cycle
counter using the multi-cycle counter write command
in the absence of an external absolute system is as
follows:
1. Host sends a null write (wm = 0) command with
rm = 0 (position and status read) or rm = 3 (regis-
ter value and angle read) in the SPI control byte.
2. Host sends another command while reading back
the response packet.
3. Host sends a multi-cycle counter write command
(wm = 1) with the new multi-cycle counter value
and mcs = step 2 response packet bit 9.
See SPI Communication on page 29 for more infor-
mation. If an external absolute system supplies the
multi-cycle counter synchronization bit, steps 1 and 2
above are omitted.
The multi-cycle counter atomic read/write command
presets the multi-turn counter and reads back the sen-
sor/angle at the same instant to verify that the multi-cy-
cle counter was properly preset.
The complete sequence for presetting the multi-cycle
counter using the multi-cycle counter atomic read/write
command in the absence of an external absolute sys-
tem is as follows:
1. Host sends a null write (wm = 0) command with
rm = 0 (position and status read) or rm = 3 (reg-
ister value and position read) in the SPI control
byte.
2. Host sends another command while reading back
the response packet.
3. Host sends a multi-cycle counter atomic write
command (wm = 2) with the new multi-cycle
counter value and mcs = step 2 response packet
bit 9.
4. Host sends a null write (wm = 0) command with
rm = 0 (position and status read) or rm = 3 (reg-
ister value and position read) in the SPI control
byte. The multi-cycle counter is preset at the
same instant as the position is read.
5. Host sends another command while reading back
the response packet. The returned sensor angle
is the angle indicated by the sin/cos inputs when
the multi-turn counter was preset.
6. Host verifies that the sin/cos input sector (half-pe-
riod) when the multi- turn counter was preset was
correct. If not, the multi-cycle counter must be
preset again.
See SPI Communication on page 29 for more infor-
mation. If an external absolute system supplies the
multi-cycle counter synchronization bit, steps 1 and 2
above are omitted.