IC-TW28 Datasheet, PDF (60/80 Pages) IC-Haus GmbH – 10-BIT SIN/COS INTERPOLATOR

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Rev D2, Page 60/80
The complete status and fault logic of the iC-TW28 is that these bits function as switches or gates as shown
shown in Figure 34. Bits shown with an "X" indicate in Figure 33.
STAT_VAL
Read-only Status
STAT_LATCH
Latched Status
(write to clear)
STAT_SEL X X X X X X X X
STAT_IE X X X X X X X X
Interrupt Source Select
Interrupt
Enable
STAT_HIZ X X X X X X X X
STAT_FATAL 0 0 0 0 0
Multi-Cycle Counter Rollover
Z Capture Event
STAT_CFG 0 0 X X filter
irq (SPI Status Byte)
xIRQ
ABZ Output Disable (Hi-Z)
Figure 34: iC-TW28 Status and Fault Logic
The STAT_FATAL register contains three bits that in- iC-TW28 by toggling the reset input (xRST) or by using
dicate fatal internal conditions (interrupt error, eeprom the start/restart command. See COMMAND on page
double-bit error, eeprom checksum error). If any of 50.
these conditions are active, the iC-TW28 activates the
irq (SPI Status Byte)
ionutetprruutp(txrIeRqQu_Se)_{T,sAat Tnb_ditV}(di_Ariqs_L)a_.,_{xbalectsivtahteesAtBheZinotuetrpruuptst}
request
(output
A position capture event_xIa_Rn_Qd/or multi-cycle counter
shutdown_S, _To_Au_Ttp_{_}u_Lt_Atr_Tis_Cta_Hte_.x).
rollover can also be configured to interrupt the host pro-
STAT_IE.x ^{cessor. STAT_CFG.enc enables an interrupt when the}
In stand-alone applications_S, _Tth_Ae_Ts_{_}e_Sf_Eat_La_.l_xfault conditions multi-cycle counter rolls over; STAT_CFG.enz enables
must be cleared by cycling power to the iC-TW28. In an inter_Ar_Bup_Zt_Oo_un_tpa_up_{t D}os_isi_ati_bo_ln_e c_(Hap_i-Ztu₎re event (as configured
hosted applications, the host processor can reset the by ZERO0.mode).
STAT_HIZ.x