HY27US08121M Datasheet, PDF (22/43 Pages) Hynix Semiconductor – 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash

HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Sequential Row Read Disabled
If the device is delivered with Sequential row read disabled and Automatic Read Page 0 at Power-up, only the first
page (Page 0) will be automatically read after the power-on sequence. Refer to Figure 18.
Sequential Row Read Enabled
If the device is delivered with the Automatic Page 0 Read option only (Sequential Row Read Enabled), the device will
automatically enter Sequential Row Read mode after the power-up sequence, and start reading Page 0, Page 1, etc.,
until the last memory location is reached, each new page being accessed after a time t_BLBH1.
The Sequential Row Read operation can be inhibited or interrupted by de-asserting E (set to V_IH) or by issuing a com-
mand. Refer to Figure 19.
Note: (1). V_CCth is equal to 2.5V for 3.3V Power Supply devices and to 1.5V for 1.8V Power Supply devices.
Vccth (1)
Vcc
WE
CE
ALE
CLE
RB
tBLBH1
RE
I/O
Busy
Data
N
Data
N+1
Data
N+2
Last
Data
Data Output
from Address N to Last Byte or Word in Page
Figure 18. Sequential Row Read Disabled and Automatic Page 0 Read at power-up
Rev 0.6 / Oct. 2004
22