HD49235FS Datasheet, PDF (9/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
Register 9
D7
BI1
D6
BI0
D5
WG10TL D4
SYLCK1 D3
SYLCK0 D2
CRCQ
D1
0
1
Illegal setting
Normal operation
00: Normal play
01: Double-speed play
10: Quadruple-speed play 11: Quadruple-speed play
Sync detection window width: ±10 T
Sync detection window width: ±19 T
Length of time sync lock state is maintained when sync signal is missing
00: 2 frames 01: 4 frames
10: 8 frames 11: 12 frames
QOK flag is not inserted in QDATA output QOK flag is inserted in QDATA output
Register A
0
1
MUTEL
D7 Left-channel mute off
Left-channel mute on
MUTER D6 Right-channel mute off
Right-channel mute on
MONO
D5 Stereo
Monaural
ATT
D4 Attenuation off
Attenuation (–12 dB) on
BLGMAIN D3 00: Stereo
01: Bilingual, right channel
BLGSUB D2 10: Bilingual, left channel 11: Bilingual, left channel
SOFTMT D1 Soft mute off
Soft mute on
SWLR
D0 Normal
Left-right reverse
Notes: 1. Priority for mute and attenation as follows.
“Mute” port > SOFTMT > MUTE L, MUTE R > ATT
2. In the case of setting “ROM” = 1 (CD-ROM mode), the data of register “A” is ignored and is
considered all zero.
It is recovered as it were, after setting “ROM” = 0.
3. “BLGMAIN” and “BLG SUB” commands are ignored if “SWLR” = 1, and set stereo.
Register B
Track counter setting
D7
D6
D5
D4
D3
D2
D1
D0
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
128 64
32
16
8
4
2
1
Rev.2, Aug. 1995, page 9 of 41