HD49235FS Datasheet, PDF (8/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
Microprocessor Commands
Data
SENS
Register
Pin
(Address) Command D7
D6
D5
D4
D3
D2
D1
D0
Output
8 (1000) Mode
ROM
selections
ROMEF DOOFF SUBCO SLTSW 0
DCOND DWIDTH Z
9 (1001) Function 1
BI1
BI0
WG10TL SYLCK1 SYLCK0 CRCQ *
Z
selections
A (1010) Audio
control
MUTEL MUTER MONO ATT
BLGMAIN BLGSUB SOFTMT SWLR Z
B (1011) Track
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
Complete
counter
setting
C (1100) CLV control AINTV ATH
GAIN1 GAIN0 SGAIN1 SGAIN0 PDGAIN1 PDGAIN0 Count
D (1101) CLV kick KICK7 KICK6 KICK5 KICK4 KICK3 KICK2 KICK1 *
Z
control
E (1110) CLV mode ED3
ED2
ED1
ED0
0
*
*
*
BRAKE
F (1111) ECU mode 0
0
AS0
*
*
*
*
*
Z
Asterisks indicate don’t-care bits
Register 8
ROM
D7
ROMEF D6
DOOFF D5
SUBCO D4
SLTSW D3
D2
DCOND D1
DWIDTH D0
0
1
Audio (with interpolation)
CD-ROM (no interpolation)
C2 flag output order: lower first
C2 flag output order: upper first
Digital output on
Digital output off
Subcode data not inserted in DAS signal Subcode data inserted in DAS signal
48-fs clock
64-fs clock
Normal operation
Illegal setting
Condition for switching between digital and Condition for switching between digital and
analog PLLs: digital PLL when defect
analog PLLs: digital PLL when defect
detection signal width is 4 frames or more detection signal width is 8 frames or more
Digital PLL termination timing:
• 8 frames after fall of defect detection • 4 frames after fall of defect detection
signal if width of defect detection signal signal if width of defect detection signal
width is less than 12 frames
width is less than 12 frames
• 16 frames after fall of defect detection • 8 frames after fall of defect detection
signal if width of defect detection signal signal if width of defect detection signal
width is 12 frames or more
width is 12 frames or more
Rev.2, Aug. 1995, page 8 of 41