HD49235FS Datasheet, PDF (10/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
Register C
AINTV
D7
ATH
D6
GAIN1
D5
GAIN0
D4
SGAIN1 D3
SGAIN0 D2
PDGAIN1 D1
PDGAIN0 D0
0
1
Sync detection count is tested at 32-frame Sync detection count is tested at 64-frame
intervals
intervals
Sync must be detected 4 times or more Sync must be detected 8 times or more
Speed error (PWM pin output) gain in CLV steady state operation
00: –6 dB 01: 0 dB
10: +6 dB 11: 0 dB
Speed error gain and access
00: –6 dB 01: 0 dB
10: +6 dB 11: 0 dB
CLV phase error (MSTOP pin output) gain
00: –6 dB 01: 0 dB
10: +6 dB 11: 0 dB
Register D
D7
D6
D5
D4
D3
D2
D1
D0
CLV kick control
KICK7 KICK6 KICK5 KICK4 KICK3 KICK2 KICK1 *
(PWM duty cycle)
64/128 32/128 16/128 8/128 4/128 2/128 1/128 *
Asterisks indicate don’t-care bits
Rev.2, Aug. 1995, page 10 of 41