HD49235FS Datasheet, PDF (17/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
EFM Demodulation
After being processed in the data strobe block, the EFM signal is converted to NRZ by an NRZ-I
conversion using a PLL-synchronized clock signal (PLL clock, 4.3218 MHz when the PLL is locked in
standard speed playback mode).
The 24-bit frame synchronization signal is detected from this EFM signal. Operation of the EFM
demodulation block is timed according to the occurrence of the frame synchronization signal.
Due to disc defects and other causes, frame synchronization signals may sometimes be detected at false
positions in the EFM signal read from the disc. The sync protection block therefore opens a window around
the time when the correct synchronization signal is expected, and frame synchronization signals are used
for timing purposes only if they are detected within this window.
If the frame synchronization signal is not detected, it is automatically interpolated at the time when the
correct frame synchronization signal would be expected to occur. Detection and interpolation of the frame
synchronization signal will be described in detail in the description of the sync protection block.
After being converted to NRZ form, the EFM signal is converted to 14-bit parallel data by the EFM
demodulation block. This conversion is timed to the occurrence of the above frame synchronization signal.
Next, 14-bit-to-8-bit demodulation is performed: the 14-bit parallel data is fed to the EFM demodulation
ROM and converted to 8 bits.
After EFM demodulation, the 8-bit data is separated into subcode data, which is passed to the subcode
signal-processing block, and audio data, which is output to the internal data bus. The data bus is connected
to the error correction unit (ECU) and the RAM control block.
Subcode Signal Processing
S1: The CD format groups subcode data into 98-frame blocks. Each block begins with two subcode
synchronization signals: S0 and S1. In this chip, S0 and S1 are detected in the EFM demodulation
block. S0 is delayed by one frame, then ANDed with S1, and the result (S0delay⋅S1) is output at the S1
pin.
Due to disc defects and other causes, the above S0 and S1 signals may sometimes fail to be detected.
The chip accordingly has a divide-by-98 counter that takes S0delay⋅S1 as its clear input and CFCKP* as
its clock input. When S0delay⋅S1 is not detected, it is interpolated by this counter. See figure 5.
Note: * CFCKP is derived from the PLL clock and has a frequency of 7.35 kHz (×1 speed), 14.7 kHz (×2
speed), 29.4 kHz (×4 speed) when the PLL is in lock.
Rev.2, Aug. 1995, page 17 of 41