HD49235FS Datasheet, PDF (33/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
100%
–π
0
+π
0%
Four frames
Figure 20 Duty Cycle Characteristic of MSTOP Output for Constant Linear Velocity Control
Microprocessor
command
XLT
SENS
Selecting register E
Interval between EFM edges ≥ 32 T
Figure 21 SENS Output in Brake Mode
Digital Audio Interface
BIDAT: Digital audio interface output pin. The output can be switched on or off by microprocessor
command DOOFF (in register 8).
Interpolation
A microprocessor command SLTSW (register 8) can select the 48-fs or 64-fs clock. Figures 22 and 23
show the output timing. With the 48-fs clock, a microprocessor command SUBCO (register 8) can select
whether or not to insert subcode data in the DAS output. Figures 24 and 25 show the output timing.
DAS: This pin outputs audio or ROM data. The ROM microprocessor command (in register 8) can select
whether or not to carry out interpolation. Preceding-value and mean-value interpolation are carried out.
With a 48-fs clock, the data is output MSB first and squeezed to the rear. With a 64-fs clock, the data is
output LSB first and squeezed to the rear.
CKX: This pin outputs the data transfer clock.
MPX: This pin outputs a signal that distinguishes between the left and right channels. With a 64-fs clock,
low output indicates the left channel and high output indicates the right channel. With a
48-fs clock, this polarity is reversed.
QMX: This pin outputs a clock signal with four times the frequency of MPX.
DMX: This pin outputs a clock signal with two times the frequency of MPX.
Rev.2, Aug. 1995, page 33 of 41