HD49235FS Datasheet, PDF (21/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
SUBCK: This pin inputs a subcode read clock.
Codes R to W are output together with codes P and Q. The codes are output in order, starting with the P
code, as serial data from the SUBOUT pin when read clock pulses are input at the SUBCK pin. Figure 9
shows the timing, which basically conforms to EIAJ CP-2401.
Signal Configuration: Figure 9 shows the signals output for use in display of graphics. (SF: subcode
frame)
To read the subcode data, eight subcode clock pulses (SUBCK) should be input after the fall of the
subcode frame synchronization signal (CFCKP). The data for subcode channel P is output at the fall of
CFCKP. Data in channels Q to W is output at the rise of SUBCK. See figure 10.
SF0
SF1
SF2
SF3 SF4
SF97 SF0
S1
CFCKP
*
*
*
SUBCK
SUB
OUT
*
*
*
P to W P to W P to W
Notes: Segments marked with X's are don't-care segments.
* SUBCK input during SF0 and SF1 is permissible, but the resulting output from SUBOUT
will not necessarily be correct.
Figure 9 Output Timing for Graphics Display (1)
Subcode frame (SF)
CFCKP
SUBCK
SUB
OUT
P Q RS TUV W
P
Figure 10 Output Timing for Graphics Display (2)
Rev.2, Aug. 1995, page 21 of 41