HD49235FS Datasheet, PDF (16/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
3. Data Slice Level Output
EFMI: This pin inputs the EFM RF signal.
DSLCO: This pin outputs an error signal for correcting deviation in the data slice level of the EFM
signal. This signal is used as a control signal to keep the data slice level of the EFM signal centered, by
forming a negative-feedback loop with the EFM comparator.
DSLCI: This pin inputs the above error signal through a low-pass filter to the EFM comparator.
Figure 4 shows the EFM comparator circuit. The EFM RF signal is input through a capacitive coupling,
and binarized by comparison with a slice level generated by the DSLC amplifier.
 When not in stop mode
 The DSLCO pin outputs the inverse of the binarized EFM signal. Even if the EFM signal is
asymmetrical before slicing, an appropriate slice level is obtained by feeding the dc component of
the sliced EFM signal back through an external low-pass RC filter.
 In stop mode
 The DSLCO pin outputs a square wave with a 50% duty cycle and the same period as the output at
the MPX pin, and the slice level is kept at 1/2 V_DD. This permits rapid optimization of the slice level
when the device leaves stop mode, and prevents oscillation by cutting off the loop through the low-
pass filter.
4. Control When a Defect is Detected
DEFCT: This pin inputs a disc defect detection signal. Both a digital PLL and an analog PLL are
provided on-chip. Normally the analog PLL is used, because of its good error-rate characteristic, but
when a defect detection signal is received at this pin, the chip switches over to its digital PLL for quick
pull-in after the defect disappears. After pull-in, the chip automatically switches back to its analog PLL.
UCK: This pin outputs a clock signal for the microprocessor.
UCKSL: This pin selects the frequency of the microprocessor clock (UCK). The frequency is 16.9344
MHz when UCKSL is high, and 8.4672 MHz when UCKSL is low.
MCK: This pin outputs the master clock (33.8688 MHz).
DSLCO
66
STOP
MPX
×1 ×2 ×4 speed
44.1/88.2/176.4 kHz
LPF
DSLC amplifier
1/2 V_DD
–
Amp.
–
67
DSLCI
+
Comp.
+
68
EFMI
EFM RF signal
EFM comparator
To internal circuits
EFMS
STOP
Figure 4 EFM Comparator Circuit
Rev.2, Aug. 1995, page 16 of 41