HD49235FS Datasheet, PDF (27/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
e. CLV Control (Register C)
AINTV: When a disc is played in CLV mode, the switchover between the starting servo and normal
servo modes is made automatically by testing the number of sync pulses per interval. The AINTV bit
selects the length of the interval.
ATH: When a disc is played in CLV mode, the switchover between the starting servo and normal servo
modes is made automatically by testing the number of sync pulses per interval. The ATH bit selects the
threshold number of pulses. Starting servo mode is used if the number of sync pulses detected in the
interval selected by AINTV is less than the threshold value selected by ATH. Normal servo mode is
used if the number exceeds this threshold. Only sync pulses that are validated by the sync protection
function are counted.
GAIN1 and GAIN0: These command bits select the gain of the output at the PWM pin in normal CLV
servo mode. There are three selections: –6 dB, 0 dB, and +6 dB.
SGAIN1 and SGAIN0: These bits select the PWM gain to be one of three values, –6 dB, 0 dB or 6 dB,
in start mode.
PDGAIN1 and PDGAIN0: These bits select the MSTOP pin output (CLV phase error) gain to be one
of three values, –6 dB, 0 dB or 6 dB.
f. CLV Kick Control (Register D)
KICK7 to KICK1: When kick control is enabled (by microprocessor command register E) in CLV
mode, these bits select the CLV control output pin PWM duty cycle to be one of 128 levels. For
example, to set the duty to be 74/128, set bits D7 to D0 in microprocessor control register D to be
1001010 (base 2).
PWM
*
1
*:
D₇
×
64
128
+
D₆
×
32
128
+
D₅
×
16
128
+
D₄
×
8
128
+
D₃
×
4
128
+
D₂
×
2
128
+
D₁
×
1
128
Figure 15 CLV Kick Control Output
Rev.2, Aug. 1995, page 27 of 41