HD49235FS Datasheet, PDF (28/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
g. CLV Mode (Register E)
This register determines the constant linear velocity control mode. Command data written in bits D7 to
D4 (ED3 to ED0) of register E selects stop, play, rotate, kick, brake, access, start, or normal mode. For
details of these operating modes, see the description of the CLV servo block.
h. ECU Mode (Register F)
The error-correcting capability of the error-correcting unit (ECU) can be selected. Correction when a
track jump occurs can be limited to two symbols at the C1 level and three symbols at the C2 level by
setting bit AS0 to 1, to reduce the likelihood of false corrections.
Sync Protection Block
The pulse width of the EFM signal read from the disc is measured, using the crystal oscillator clock as a
time base. The pulse width value is used to detect the synchronization pattern consisting of the first 24 bits
in each frame, and produce a synchronization pulse named ASYNC.
Due to disc defects and other causes, ASYNC may be detected in an incorrect position, so a divide-by-576
counter* is used to establish a window, and only ASYNC pulses detected within this window are regarded
as valid synchronization pulses (referred to as valid ASYNC pulses). Other synchronization pulses are
disregarded. The width of this window can be set to one of two values by the microprocessor command
WG10TL as follows.
WG10TL = 0: The window width is set to ±10T (±1.7%)
WG10TL = 1: The window width is set to ±19T (±3.1%)
Valid ASYNC pulses occur with correct synchronization timing, but they may sometimes be missing, e.g.
because of rejection of pulses outside the detection window. Where valid ASYNC pulses are missing,
PSYNC pulses are generated by interpolation. Valid ASYNC and PSYNC are the basic constant linear
velocity control signals used in the CLV motor control circuit.
When two consecutive valid ASYNC pulses are detected, the chip assumes that it has acquired
synchronization lock and drives the SLOCK pin high.
If valid ASYNCs are not detected for a consecutive number of times set by the SYLCK0 and SYLCK1
microprocessor command bits, interpolation is stopped and the SLOCK pin is driven low.
When (SYLCK1, SYLCK0) are (0, 0): if ASYNCs are missing for 2 consecutive times interpolation is
stopped and the SLOCK pin goes low.
When (SYLCK1, SYLCK0) are (0, 1): if ASYNCs are missing for 4 consecutive times interpolation is
stopped and the SLOCK pin goes low.
When (SYLCK1, SYLCK0) are (1, 0): if ASYNCs are missing for 8 consecutive times interpolation is
stopped and the SLOCK pin goes low.
When (SYLCK1, SYLCK0) are (1, 1): if ASYNCs are missing for 12 consecutive times interpolation is
stopped and the SLOCK pin goes low.
Figure 17 is a timing diagram for the valid ASYNC and SLOCK relationships for the case where detection
of two consecutive missing valid ASYNCs was specified by microprocessor command.
Note: * 4.2336 MHz/576 = 7.35 kHz (standard speed playback)
Rev.2, Aug. 1995, page 28 of 41