HD49235FS Datasheet, PDF (3/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
Pin Description
Pin
No. Symbol Name
I/O*
1 XRST X (µ-com)
I
reset
2 CNIN
Counter clock I
input
3 SENS Sensor
TO
4 DATA Data
I
5 CLK
Clock
I
6 XLT
X (µ-com) latch I
7 V_SS (D) V_SS (digital)
—
8 OVFW RAM- overflow O
9 S1
Subcode sync O
1
10 QOK Q-code OK O
11 QDATA Q-code data O
12 CKEXT Clock-EXT I
13 SUBOUT Subcode out O
14 SUBCK Subcode clock I
15 CFCKP C&D frame O
clock out
16 EMP
17 BIDAT
18 MUTE
19 DAS
Emphasis
O
output
Biphase date TO
Mute
I
Data serial out O
20 CKX
Clock X
O
Connection Function
Microprocessor Microprocessor interface
register reset
Servo IC
Pulse input for track counter
Polarity
H
L
Reset
Microprocessor Servo status output
Microprocessor Data input for microprocessor
interface
Microprocessor Clock input for microprocessor
interface
Microprocessor Strobe input for
microprocessor interface
Digital ground
On-chip RAM overflow signal
output
Microprocessor Subcode sync signal
(with protection)
Microprocessor Subcode CRC result output OK
Microprocessor Subcode Q data output
Microprocessor Clock input for Q data readout
CD graphics
Subcode data output for CD
graphics
CD graphics
Clock input for SUBOUT
subcode readout
CD graphics
Subcode frame
synchronization signal (7.35
kHz at normal speed,
synchronized with PLL)
Emphasis on/off status output ON
Overflow
NG
OFF
Digital audio interface output
Microprocessor Audio mute input
Mute
DAC or ROM Serial data output for audio or
decoder
ROM
DAC or ROM Strobe clock output for DAS
decoder
signal
Rev.2, Aug. 1995, page 3 of 41