HD49235FS Datasheet, PDF (19/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
QDATA: This is the output pin for the Q subcode data.
QDSEL: This pin selects one of the following two modes.
a. Q code buffer mode (selected when QDSEL is low)
When the QDSEL pin is low, the chip uses its 80-bit Q code buffer function, and outputs the Q
subcode from the QDATA pin in synchronization with an external clock signal (for example, a
clock signal from a microprocessor).
As shown in figure 6, the chip has two 80-bit registers. While Q code data is being written in one
register, the Q code can be read from the other register asynchronously, by input of clock signals
from the microprocessor at the CKEXT pin. This feature places less of a load on the microprocessor.
To switch between reading and writing of the shift registers, the S1 and QOK signals are ANDed, so
before sending clock pulses for input to CKEXT, the microprocessor should check for the fall of S1,
then check that QOK is high (indicating that the cyclic redundancy check of the Q data passed).
These checks will enable the Q subcode to be read correctly.
The 80-bit shift register is designed to store data in 4-bit nibbles, LSB first. If the microprocessor
inputs serial data in LSB-first form, it does not have to rearrange the 4 bits.
Figure 7 shows the timing chart.
b. Q code internal synchronization mode (selected when QDSEL is high)
When the QDSEL pin is high, a Q code strobe clock generated in the HD49235 is output from the
CFCKP pin, and the Q code is output from the QDATA pin at a rate of one bit per frame,
synchronized with the strobe clock (CFCKP). This is referred to as Q code internal synchronization
mode. Figure 8 shows the timing.
S1 · QOK
Subcode
4-bit
Q
rearrangement
80-bit shift register
CK
QDATA
CKEXT
80-bit shift register
CK
Figure 6 Block Diagram of Q Code Buffer When QDSEL is Low
Rev.2, Aug. 1995, page 19 of 41