HD49235FS Datasheet, PDF (34/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
C2F: This output pin goes high to flag data errors that could not be corrected by C2 error correction. C2F is
low when there are no such uncorrectable errors. C2F is synchronized to the data output on the DAS line.
When audio is selected by the ROM microprocessor command, this signal is output once for every two
bytes on the left and right channels. When CD-ROM is selected, the signal is output once per byte (every 8
bits).
See figure 26 for the output timing.
MUTE: Selects whether to mute the audio data.
Low: Muting is not performed.
High: Muting is performed.
When MUTE goes high, the address control circuit is initialized so as to maximize the RAM frame jitter
margin at that point. This initialization is performed continuously while MUTE is high. Normal
reproduction resumes when MUTE goes low.
Other Pins
MRST: Master reset. The HD49235FS chip resets when MRST goes low, and operates normally when
MRST is high. This pin has a pull-up resistor, so it can be either left open or connected to V_DD.
TEST1 to TEST3: These pins input test control signals. These pins have pull-up resistors, so they can be
either left open or connected to V_DD.
V_DD: Power supply pin.
V_SS: Ground pin.
NC: These pins should be left unconnected. Correct operation is not assured if they are connected.
Rev.2, Aug. 1995, page 34 of 41