HD49235FS Datasheet, PDF (15/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
c. Next, reproduction from the disc will begin. When the microprocessor sends command data to start
disc rotation, the disc stop signal is turned off.
Switch (A) is now connected to receive a 4.2336 MHz clock from the crystal oscillator and counter
(A) is changed to be a divide-by-96 counter. The counter (A) output is held at 44.1 kHz by
switching the divisor. Here, switching is performed on the counter (A) output edge. The phase error
existing between the VCO and the crystal oscillator clock (the phase error that was detected at
adjustment step 2) is maintained.
d. When the disc is rotating and reproduction starts, switch (B) is connected to receive the EFM signal.
The phase detector PDOUT1 in figure 2 compares the phases of the EFM signal, which was
converted to binary by the EFM comparator, and the bit clock and outputs phase comparison
information from the PDOUT1 pin.
As shown in figure 3, when the EFM signal is in phase with the clock produced by the VCO, the
PDOUT1 output is high and low for equal lengths of time. When the EFM signal leads the on-chip
VCO clock, the high length is longer than the low length. When the EFM signal lags the on-chip
VCO clock, the high length is shorter.
EFMI
Bit clock
PDOUT1
EFMI
Bit clock
PDOUT1
EFMI
Bit clock
PDOUT1
(In phase)
High impedance
(Phase leads)
High impedance
(Phase lags)
High impedance
Figure 3 Timing of PDOUT1 Output Signal
Rev.2, Aug. 1995, page 15 of 41