HD49235FS Datasheet, PDF (35/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
MPX
8 bit
16 bit
DAS
R0
L1-MSB
L1
R1-MSB
R1
L2-MSB
L2
CKX
(2.12 MHz)
Figure 22 Audio/ROM Data Output Sequence (When 48-fs Clock is Selected):
DAS Switched at Fall of CKX
MPX
16 bit
16 bit
DAS
R0
L1-LSB
L1
R1-LSB
R1
L2-LSB
L2
CKX
(2.82 MHz)
Figure 23 Audio/ROM Data Output Sequence (When 64-fs Clock is Selected):
DAS Switched at Rise of CKX
MPX
8 bit
DAS
R0
F/B
SYNC
L1
SUB
CODE
R1
F/B
SYNC
L2
CKX
(2.12 MHz)
Figure 24 Audio/ROM Data Output Sequence with Subcode Data Inserted (When 48-fs
Clock is Selected): DAS Switched at Fall of CKX
1 frame
DAS ^{R5 L0 R0 L1 R1 L2 R2 L3 R3 L4 R4 L5 R5 L0 R0 L1 R1}
FSYNC
(a) FSYNC Timing
1 frame
1 sector
DAS ^{S96 S97 S0 S1 S2 S3 . . . S96 S97 S0 S1 S2}
FSYNC
In audio mode,
FSYNC goes
low at the timing
of the L2 data
BSYNC
(b) F/B SYNC Timing
Figure 25 F/B SYNC Signal Timing Diagram
Rev.2, Aug. 1995, page 35 of 41