HD49235FS Datasheet, PDF(26/41 Page) Hitachi Semiconductor

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD49235FS Datasheet, PDF (26/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

◁

HD49235FS

d. Track Counter Setting (Register B)

An internal counter counts the track-crossing signal input at the CNIN pin. When the count reaches the

value set in register B, the SENS output inverts.

Depending on the order in which registers B and C are set, tracks are counted in complete mode (once

only) or count mode (repeatedly). See the timing diagram in figure 14.

ï£§ Complete mode

Step 1: Set desired values in all registers other than registers B and C.

Step 2: Set register C.

Step 3: Set the count value in register B.

Step 4: Monitor the SENS line at the microprocessor.

Microprocessor

command

Step 1

XLT

Step 2

Step 3 Step 4

CNIN

Complete mode

SENS

Count mode

n counts

Figure 14 Track Counting

ï£§ Count mode

Step 1: Same as complete mode.

Step 2: Set the count value in register B.

Step 3: Set register C.

Step 4: Monitor the SENS line at the microprocessor.

Notes: 1. Do not use the microprocessor interface while the microprocessor is monitoring the SENS line.

2. If all zeros are written in register B, the count setting is 256.

3. Do not monitor the SENS pin between steps 2 and 3.

Rev.2, Aug. 1995, page 26 of 41

▷