HD49235FS Datasheet, PDF (29/41 Pages) Hitachi Semiconductor – Digital Signal Processor for CD

HD49235FS
SLOCK: This output pin indicates whether sync signals were detected correctly during disc playback.
This signal goes high when correct sync signals are detected in two consecutive frames, and goes low
when sync signals are missing consecutively for the number of times specified by the SYLCK0 and
SYLCK1 microprocessor command bits.
PWL
PWH
Sync pattern
Figure 16 Sync Pattern at Start of Frame
Valid ASYNC missing
×
Valid ASYNC
SLOCK
Valid ASYNC
×
Goes high when valid
ASYNC is detected
twice consecutively
×
×
×
Goes low when valid ASYNC is missing
consecutively a number of times
selected by microprocessor command
bits SYLCK0 and SYLCK1*
Note: * This figure is for the case when two consecutive missing ASYNCs is specified.
Figure 17 Valid ASYNC and SLOCK Relationships
Rev.2, Aug. 1995, page 29 of 41