GS4288C09 Datasheet, PDF (6/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
Ball Descriptions (Continued)
Symbol
QVLD
Type
Output
Description
Data Valid—The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx.
TDO
Output
IEEE 1149.1 Test Output—JTAG output. This ball may be left as no connect if the JTAG function is not
used.
V_DD
Supply
Power Supply—Nominally, 1.8 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
V_DDQ
Supply
DQ Power Supply—Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See
the DC Electrical Characteristics and Operating Conditions section for range.
V_EXT
Supply
Power Supply—Nominally, 2.5 V. See the DC Electrical Characteristics and Operating Conditions
section for range.
V_SS
Supply Ground
V_TT
—
Power Supply—Isolated termination supply. Nominally, V_DDQ/2. See the DC Electrical Characteristics
and Operating Conditions section for range.
A21, A22
—
Reserved for Future Use—This signal is not connected and may be connected to ground.
DNU
—
Do Not Use—These balls may be connected to ground.
NF
—
No Function—These balls can be connected to ground.
Operations
Initialization
A specific power-up and initialization sequence must be observed. Other sequences may result in undefined operations or
permanent damage to the device.
Power-up:
1. Apply power (V_EXT, V_DD, V_DDQ, V_REF, V_TT) . Start clock after the supply voltages are stable. Apply V_DD and V_EXT before or
at the same time as V_DDQ¹. Apply V_DDQ before or at the same time as V_REF and V_TT. The chip starts internal initlization
only after both voltages approach their nominal levels. CK/CK must meet V_ID(DC) prior to being applied². Apply only
NOP commands to start. Ensuring CK/CK meet V_ID(DC) while loading NOP commands guarantees that the LLDRAM II
will not receive damaging commands during initialization.
2. Idle with continuing NOP commands for 200s (MIN).
3. Issue three or more consecutive MRS commands: two or more dummies plus one valid MRS. The consecutive MRS
commands will reset internal logic of the LLDRAM II. tMRSC does not need to be met between these consecutive
commands. Address pins should be held Low during the dummy MRS commands.
Rev: 1.03 7/2014
6/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology