GS4288C09 Datasheet, PDF (41/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
AC Differential Input Clock Levels
Parameter
Symbol
Min.
Max.
Unit
Notes
Clock input differential voltage: CK and CK
V_ID(AC)
0.4
V_DDQ + 0.6
V
1–5
Clock input crossing point voltage: CK and CK
V_IX(AC)
V_DDQ/2 – 0.15
V_DDQ/2 + 0.15
V
1–4, 6
Notes:
1. DKx and DKx have the same requirements as CK and CK.
2. All voltages referenced to V_SS (GND).
3. The CK and CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross. The input reference level for
signals other than CK/CK is V_REF.
4. The CK and CK input slew rate must be  2 V/ns ( 4 V/ns if measured differentially).
5. V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
6. The value of V_IX is expected to equal V_DDQ/2 of the transmitting device and must track variations in the DC level of the same.
V_{IN(DC) MAX}
CK
Differential Clock Input Requirements
Maximum Clock Level
V_DDQ/2 + 0.15
V_DDQ/2
V_DDQ/2 – 0.15
V_IX(AC)MAX
1
V_IX(AC)MIN
V_ID(DC)2
V_ID(AC)3
CK
V_{IN(DC) MIN}
Minimum Clock Level
Notes:
1. CK and CK must cross within this region.
2. CK and CK must meet at least V_ID(DC)MIN when static and centered around V_DDQ/2.
3. Minimum peak-to-peak swing.
4. It is a violation to tristate CK and CK after the part is initialized.
Rev: 1.03 7/2014
41/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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