GS4288C09 Datasheet, PDF (51/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
Test-Logic-Reset
The test-logic-reset controller state is entered when TMS is held High for at least five consecutive rising edges of TCK. As long as
TMS remains High, the TAP controller will remain in the test-logic-reset state. The test logic is inactive during this state.
Run-Test/Idle
The run-test/idle is a controller state in between scan operations. This state can be maintained by holding TMS Low. From here
either the data register scan, or subsequently, the instruction register scan can be selected.
Select-DR-Scan
Select-DR-scan is a temporary controller state. All test data registers retain their previous state while here.
Capture-DR
The Capture-DR state is where the data is parallel-loaded into the test data registers. If the Boundary Scan Register is the currently
selected register, then the data currently on the pins is latched into the test data registers.
Shift-DR
Data is shifted serially through the data register while in this state. As new data is input through the TDI pin, data is shifted out of
the TDO pin.
Exit1-DR, Pause-DR, and Exit2-DR
The purpose of Exit1-DR is used to provide a path to return back to the run-test/idle state (through the Update-DR state). The
Pause-DR state is entered when the shifting of data through the test registers needs to be suspended. When shifting is to reconvene,
the controller enters the Exit2-DR state and then can re-enter the Shift-DR state.
Update-DR
When the EXTEST instruction is selected, there are latched parallel outputs of the boundary scan shift register that only change
state during the Update-DR controller state.
Instruction Register States
The instruction register states of the TAP controller are similar to the data register states. The desired instruction is serially shifted
into the instruction register during the Shift-IR state and is loaded during the Update-IR state.
Loading Instruction Code and Shifting Out Data
T0
T1
TCK
TMS
TDI
TAP State
Logic-Reset
Idle
TDO
T2
T3
T4
T5
T6
T7
T8
T9
8-bit Instruction Code
Select-DR
Select-IR
Capture-IR
Shift-IR
Shift-IR
Exit 1-IR
Pause-IR
Pause-IR
Rev: 1.03 7/2014
51/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology