GS4288C09 Datasheet, PDF (2/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

32M x 9 Mb Ball Assignments—144-Ball BGA—Top View
GS4288C09/18/36L
1
2
3
4
5
6
7
8
9
10
A
V_REF
V_SS
V_EXT
V_SS
V_SS
V_EXT
B
V_DD
DNU³ DNU³
V_SS
V_SS
DQ0
C
V_TT
DNU³ DNU^{3 V}DDQ
V_DDQ
DQ1
D
A22¹ DNU³ DNU³
V_SS
V_SS
QK0
E
A21¹ DNU³ DNU^{3 V}DDQ
V_DDQ
DQ2
F
A5
DNU³ DNU³
V_SS
V_SS
DQ3
G
A8
A6
A7
V_DD
V_DD
A2
H
B2
A9
V_SS
V_SS
V_SS
V_SS
J
NF²
NF²
V_DD
V_DD
V_DD
V_DD
K
DK
DK
V_DD
V_DD
V_DD
V_DD
L
REF
CS
V_SS
V_SS
V_SS
V_SS
M
WE
A16
A17
V_DD
V_DD
A12
N
A18
DNU³ DNU³
V_SS
V_SS
DQ4
P
A15
DNU³ DNU^{3 V}DDQ
V_DDQ
DQ5
R
V_SS
DNU³ DNU³
V_SS
V_SS
DQ6
T
V_TT
DNU³ DNU^{3 V}DDQ
V_DDQ
DQ7
U
V_DD
DNU³ DNU³
V_SS
V_SS
DQ8
V
V_REF
ZQ
V_EXT
V_SS
V_SS
V_EXT
Notes:
1. Reserved for future use. This pin may be connected to ground.
2. No function. This pin may have parasitic characteristics of a clock input signal. It may be connected to GND.
3. Do not use. This pin may have parasitic characteristics of an I/O. It may be connected to GND.
11
12
TMS TCK
DNU³
V_DD
DNU³
V_TT
QK0
V_SS
DNU^{3 A20}
DNU^{3 QVLD}
A1
A0
A4
A3
B0
CK
B1
CK
A14
A13
A11
A10
DNU^{3 A19}
DNU³
DM
DNU³
V_SS
DNU³
V_TT
DNU³
V_DD
TDO
TDI
Rev: 1.03 7/2014
2/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology