GS4288C09 Datasheet, PDF (47/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
AC Electrical Characteristics
Parameter
Symbol
–18
Min
Max
Clock
Input Clock Cycle Time
tCK
1.875
5.7
Input data clock cycle time
tDK
tCK
Clock jitter: period
tJIT_PER
–100
100
Clock jitter: cycle-to-cycle
tJIT_CC
—
200
Clock High Time
tCKH
tDKH
0.45
0.55
Clock Low Time
tCKL
tDKL
0.45
0.55
Clock to input data clock
tCKDK
–0.3
0.3
Mode register set cycle time
to any command
tMRSC
6
—
Setup Times
Address/command and input
setup time
tAS/tCS
0.3
—
Data–in and data mask to
DK set up time
tDS
0.17
—
Hold Times
Address/command and input
hold time
tAH/tCS
0.3
—
Data-in and data mask to
DK setup time
tDH
0.17
—
Data and Data Strobe
Output data clock High time tQKH
0.9
1.1
Output data clock Low time tQKL
0.9
1.1
Half–clock period
tQHP
MIN
(tQKH, tQKL)
—
QK edge to clock edge skew tCKQK
–0.2
0.2
QK edge to output data
edge
tQKQ0,
tQKQ1
–0.12
0.12
QK edge to any output data
edge
tQKQ
–0.22
0.22
QK edge to QVLD
tQKVLD
–0.22
0.22
Data Valid Window
tDVW
tDVW (MIN)
—
–24
Min
Max
2.5
5.7
tCK
–150
150
—
300
0.45
0.55
0.45
0.55
–0.45
0.5
6
—
0.4
—
0.25
—
0.4
—
0.25
—
0.9
1.1
0.9
1.1
MIN
(tQKH, tQKL)
—
–0.25
0.25
–0.2
0.2
–0.3
0.3
–0.3
0.3
tDVW (MIN)
—
–25
Min
Max
2.5
5.7
tCK
–150
150
—
300
0.45
0.55
0.45
0.55
–0.45
0.5
6
—
0.4
—
0.25
—
0.4
—
0.25
—
0.9
1.1
0.9
1.1
MIN
(tQKH, tQKL)
—
–0.25
0.25
–0.2
0.2
–0.3
0.3
–0.3
0.3
tDVW (MIN)
—
–33
Min
Max
3.3
5.7
tCK
–200
200
—
400
0.45
0.55
0.45
0.55
–0.45
1.2
6
—
0.5
—
0.3
—
0.5
—
0.3
—
0.9
1.1
0.9
1.1
MIN
(tQKH, tQKL)
—
–0.3
0.3
–0.25
0.25
–0.35
0.35
–0.35
0.35
tDVW (MIN)
—
ns —
ns —
ps 5, 6
ps —
tCK —
tCK —
ns —
tCK —
ns —
ns —
ns —
ns —
t_CKH —
t_CKL —
——
ns —
ns 7
ns 8
ns —
—9
Rev: 1.03 7/2014
47/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology