GS4288C09 Datasheet, PDF (27/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
Auto Refresh
The Auto Refresh (AREF) command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are
generated by an internal refresh counter, so address inputs are Don’t Care, but a bank addresses (BA 2:0) must be provided during
the AREF command. A refresh may be contining in one bank while other commands, including other AREF commands, are
launched in other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must
be at least tRC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 288Mb device requires 64K refresh cycles at an
average periodic interval of 0.49s MAX (actual periodic refresh interval is 32 ms/8K rows/8 banks = 0.488s). To improve
efficiency, eight AREF commands (one for each bank) can be launched at periodic intervals of 3.90s (32 ms/8K rows = 3.90s).
The Auto Refresh Cycle diagram illustrates an example of a refresh sequence.
Auto Refresh (AREF) Command
CK
CK
CS
WE
REF
A(20:0)
BA(2:0)
BA
Auto Refresh Cycle
CK
CK
CMD
AREF
Bank
BA0
AREF
BA3
NOP
AREF
BA4
Rev: 1.03 7/2014
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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