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GS4288C09 Datasheet, PDF (45/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II
GS4288C09/18/36L
Capacitance
Description
Address/control input capacitance
Input/Output capacitance (DQ, DM, and QK, QK)
Clock capacitance (CK/CK and DK/DK)
JTAG pins
Notes:
1. Capacitance is not tested on the ZQ pin.
2. JTAG Pins are tested at 50 MHz.
Symbol
CI
CO
CCK
CJTAG
Conditions
TA = 25° C; f = 100 MHz
VDD = VDDQ = 1.8 V
Min.
Max.
Unit
1.0
2.0
pF
3.0
4.5
pF
1.5
2.5
pF
1.5
4.5
pF
IDD Operating Conditions
Description
Standby Current
Active Standby Current
Operational Current
Operational Current
Operational Current
Burst Refresh Current
Condition
Symbol
-18 -24 -25 -33
tCK = idle, All banks idle; No inputs
toggling.
CS = 1, No commands; Bank address
incremented and half address/data change
once every four clock cycles.
BL = 2, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by Write sequence; Continuous data during
Write Commands.
ISB1 (VDD) x9/x18
ISB1 (VDD) x36
ISB1 (VEXT)
ISB2 (VDD) x9/x18
ISB2 (VDD) x36
ISB2 (VEXT)
IDD1 (VDD) x9/x18
IDD1 (VDD) x36
IDD1 (VEXT)
30 30 30 30
30 30 30 30 mA
5
5
5
5
295 270 270 250
295 270 270 250 mA
5
5
5
5
410 385 365 345
420 395 375 355 mA
15 15 15 10
BL = 4, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by Write sequence; Continuous data during
Write Commands.
IDD2 (VDD) x9/x18
IDD2 (VDD) x36
IDD2 (VEXT)
420 395 375 355
455 430 400 380 mA
25 25 25 20
BL = 8, Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC. Read followed
by Write sequence; Continuous data during
Write Commands.
IDD3 (VDD) x9/x18
IDD3 (VDD) x36
IDD3 (VEXT)
475 450 410 390
545 520 465 445 mA
40 40 40 30
Eight bank cyclic refresh; Continuous
IREF1 (VDD) x9/x18 550 475 470 415
address/data; Command bus remains in
refresh for all eight banks.
IREF1 (VDD) x36
IREF1 (VEXT)
550 475 470 415 mA
60 60 60 45
Rev: 1.03 7/2014
45/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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