GS4288C09 Datasheet, PDF (36/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
Refresh Commands in Multiplexed Address Mode
The AREF command launches a REFRESH cycle on one row in the bank addressed. Refresh row addresses are generated by an
internal refresh counter. so address inputs are Don’t Care, but Bank addresses (BA 2:0) must be provided during the AREF
command. A refresh may be continuing in one bank while other commands, including other AREF commands, are launched in
other banks. The delay between the AREF command and a READ, WRITE or AREF command to the same bank must be at least
tRC.
The entire memory must be refreshed every 32 ms (tREF). This means that this 576Mb device requires 128K refresh cycles at an
average periodic interval of 0.24s MAX (actual periodic refresh interval is 32 ms/16K rows/8 = 0.244s). To improve efficiency,
eight AREF commands (one for each bank) can be launched at periodic intervals of 1.95s (32 ms/16K rows = 1.95s). The Auto
Refresh Cycle diagram illustrates an example of a refresh sequence.
Unlike READ and WRITE commands in Address Multiplex mode, all the information needed to execute an AREF command (the
AREF command and the Band Address (BA 2:0)) is loaded in a single clock crossing, another AREF command (to a different
bank) may be loaded on the next clock crossing.
Consecutive Refresh Operations with Multiplexed Mode
T0
CK
CK
CMD AC
T1
NOP
T2
AREF
ADDR
Ax
Ay
BA BAn
BA0
Notes:
1. Any command.
2. Bank n is chosen so that tRC is met.
T3
AREF
BA1
T4
AREF
BA2
T5
AREF
BA3
T6
AREF
BA4
T7
AREF
BA5
T8
AREF
BA6
T9
AREF
BA7
T10
T11
AC
NOP
Ax
Ay
BAn
Rev: 1.03 7/2014
36/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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