GS4288C09 Datasheet, PDF (11/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
On–Die Termination (ODT)
Mode Register Bit 9 (M9) set to 1 during an MRS command enables ODT. With ODT on, the DQs and DM are terminated to V_TT
with a resistance, R_TT. Command, address, QVLD, and clock signals are not terminated. The diagram below shows the equivalent
circuit of a DQ receiver with ODT. When a tri-stated DQ begins to drive, the ODT function is briefly switched off. When a DQ
stops driving at the end of a data transfer, ODT is switched back on. Two-state DM pin never deactivates ODT.
On–Die Termination DC Parameters
Description
Symbol
Min
Max
Termination Voltage
V_TT
0.95 * V_REF
1.05 * V_REF
On–Die Termination
R_TT
125
185
Notes:
1. All voltages referenced to V_SS (GND).
2. V_TT is expected to be set equal to V_REF and must track variations in the DC level of V_REF.
3. The R_TT value is measured at 95°C T_C.
On–Die Termination–Equivalent Circuit
Units
V

Notes
1, 2
3
V_TT
SW
R_TT
Receiver
DQ
V_REF
Rev: 1.03 7/2014
11/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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