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GS4288C09 Datasheet, PDF (46/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II
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GS4288C09/18/36L
IDD Operating Conditions (Continued)
Description
Condition
Symbol
-18 -24 -25 -33
Single bank refresh; Sequential bank
IREF2 (VDD)x9/x18 350 325 320 300
Distributed Refresh Current access; Half address transitions once every IREF2 (VDD)x36
350 325 320 300 mA
tRC; Continuous data.
IREF2 (VEXT)
15 15 15 10
BL= 2; Cyclic bank access; Half of address IDD2W (VDD) x9/x18 795 680 680 585
Operating Burst Write Current bits change every clock cycle; Continuous
Example
data; Measurement is taken during
IDD2W (VDD) x36
835 715 715 620 mA
continuous Write.
IDD2W (VEXT)
60 60 60 45
BL= 4; Cyclic bank access; Half of address IDD4W (VDD )x9/x18 630 540 540 470
Operating Burst Write Current
bits change every two clock cycles;
Example
Continuous data; Measurement is taken
IDD4W (VDD) x36
735 630 630 545 mA
during continuous Write.
IDD4W (VEXT)
55 55 55 40
BL= 8; Cyclic bank access; Half of address IDD8W (VDD) x9/x18 595 510 510 445
Operating Burst Write Current
bits change every four clock cycles;
Example
Continuous data; Measurement is taken
IDD8W (VDD) x36
695 595 595 515 mA
during continuous Write.
IDD8W (VEXT)
55 55 55 40
Operating Burst Read
Current Example
BL= 2; Cyclic bank access; Half of address IDD2R (VDD)x9/x18 720 620 620 535
bits change every clock cycle; Continuous
data; Measurement is taken during
IDD2R (VDD)x36
735 630 630 545 mA
continuous Read.
IDD2R (VEXT)
60 60 60 45
Operating Burst Read
Current Example
BL= 4; Cyclic bank access; Half of address IDD4R (VDD) x9/x18 570 490 490 425
bits change every two clock cycles;
Continuous data; Measurement is taken
IDD4R (VDD) x36
675 570 570 490 mA
during continuous Read.
IDD4R (VEXT)
55 55 55 40
Operating Burst Read
Current Example
BL= 8; Cyclic bank access; Half of address IDD8R (VDD) x9/x18 555 470 470 410
bits change every four clock cycles;
Continuous data; Measurement is taken
IDD8R (VDD) x36
650 550 550 475 mA
during continuous Read.
IDD8R (VEXT)
55 55 55 40
Notes:
1. IDD specifications are tested after the device is properly initialized and is operating at worst-case rated temperature and voltage specifications.
2. Definitions of IDD Conditions:
3a. Low is defined as VIN  VIL(AC) MAX.
3b. High is defined as VIN  VIH(AC) MIN.
3c. Stable is defined as inputs remaining at a High or Low level.
3d. Floating is defined as inputs at VREF = VDDQ/2.
3e. Continuous data is defined as half the DQ signals changng between High and Low every half clock cycle (twice per clock).
3f. Continuous address is defined as half the address signals changing between High and Low every clock cycles (once per clock).
3g. Sequential bank access is defined as the bank address incrementing by one every tRC.
3h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this
is every other clock, and for BL = 8 this is every fourth clock.
3. CS is High unless a Read, Write, AREF, or MRS command is registered. CS never transitions more than once per clock cycle.
4. IDD parameters are specified with ODT disabled.
5. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related
specifications and device operations are tested for the full voltage range specified.
6. IDD tests may use a VIL-to-VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and
parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 2 V/ns in the range between VIL(AC) andVIH(AC).
Rev: 1.03 7/2014
46/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
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