GS4288C09 Datasheet, PDF (18/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
Configuration Tables
The relationship between cycle time and read/write latency is selected by the user. The configuration table below lists valid
configurations available via Mode Register bits M0, M1, and M2 and the clock frequencies supported for each setting. Write
Latency is equal to the Read Latency plus one in each configuration to reduce bus conflicts.
Cycle Time and Read/Write Latency Configuration Table
Parameter
Configuration
1²
2
3
4^{2, 3}
5
Units
tRC
4
6
8
3
5
tCK
tRL
4
6
8
3
5
tCK
tWL
5
7
9
4
6
tCK
Valid Frequency Range
266–175
400–175
533–175
200–175
333–175
MHz
Notes:
1. tRC < 20 ns in any configuration is only available with –18 and –24 speed grades.
2. BL= 8 is not available.
3. The minimum tRC is typically 3 cycles, except in the case of a Write followed by a Read to the same bank. In this instance the minimum
tRC is 4 cycles.
Rev: 1.03 7/2014
18/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology