GS4288C09 Datasheet, PDF (34/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
Read Command in Multiplexed Mode
Address Multiplexed Read data transfers are launched with a Read command, as shown below. A valid address must be provided
during the READ command. The Ax address must be loaded on the same True clock crossing used to load the READ command
and the Bank address. The Ay address and a NOP command must be provided at the next clock crossing.
Each beat of a Read data transfer is edge-aligned with the QKx signals. After a programmable Read Latency, data is available at
the outputs. One half clock cycle prior to valid data on the read bus, the data valid signal (QVLD) is driven High. QVLD is also
edge-aligned with the QKx signals. The QK clocks are free-running.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid
data edge generated at the DQ signals associated with QK0 (tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and
DQ0–DQ8 for the x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge generated at the DQ signals
associated with QK1 (tQKQ1 is referenced to DQ18–DQ35 for the x36 and DQ9–DQ17 for the x18 configuration). tQKQx is
derived at each QKx clock edge and is not cumulative over time. tQKQ is defined as the skew between either QK differential pair
and any output data edge.
At the end of a burst transfer, assuming no other commands have been initiated, output data (DQ) will go High–Z. The QVLD
signal transitions Low on the beat of a Read burst. Note that if CK/CK violates the V_ID(DC) specification while a Read burst is
occurring, QVLD remains High until a dummy Read command is issued. Back-to-back Read commands are possible, producing a
continuous flow of output data.
The data valid window specification is referenced to QK transitions and is defined as: tQHP – (tQKQ [MAX] + |tQKQ [MIN]|). See
the Read Data Valid Window section.
Any Read transfer may be followed by a subsequent Write command. The Read-to-Write timing diagram illustrates the timing
requirements for a Read followed by a Write. Some systems having long line lengths or severe skews may need additional NOP
cycles inserted between Read and Write commands to prevent data bus contention.
Read Command in Mulitplexed Mode
READ
CK
CK
CS
WE
REF
A(20:0)
Ax
Ay
BA(2:0)
BA
Rev: 1.03 7/2014
34/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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