GS4288C09 Datasheet, PDF (10/62 Pages) GSI Technology – 32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II

GS4288C09/18/36L
DLL Reset
Mode Register Bit 7 (M7) selects DLL Reset as is shown in the Mode Register Definition tables. The default setting for M7 is Low,
whereby the DLL is disabled. Once M7 is set High, 1024 cycles (5s at 200 MHz) are needed before a Read command can be
issued. The delay allows the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur
may result in a violation of the tCKQK parameter. A reset of the DLL is necessary if tCK or V_DD is changed after the DLL has
already been enabled. To reset the DLL, set M7 is Low. After waiting tMRSC, an MRS command should be issued to set M7 High.
1024 clock cycles must pass before loading the next Read command.
Driver Impedance Mapping
The LLDRAM II is equipped with programmable impedance output buffers. Setting Mode Register Bit 8 (M8) High during the
MRS command activates the feature. Programmable impedance output buffers allow the user to match the driver impedance to the
PCB trace impedance. To adjust the impedance, an external resistor (RQ) is connected between the ZQ ball and V_SS. The value of
the resistor must be five times the desired impedance (e.g., a 300 resistor produces an output impedance of 60). RQ values of
125–300 are supported, allowing an output impedance range of 25–60 (+/- 15 %).
The drive impedance of uncompensated output transistors can change over time due to changes in supply voltage and die
temperature. When drive impedance control is enabled in the MRS, the value of RQ is periodically sampled and any needed
impedance update is made automatically. Updates do not affect normal device operation or signal timing.
When Bit M8 is set Low during the MRS command, the output compensation circuits are still active but reference an internal
resistance reference. The internal reference is imprecise and subject to temperature and voltage variations so output buffers are set
to a nominal output impedance of 50, but are subject to a ±30 percent variance over the Commercial temperature range of the
device.
Rev: 1.03 7/2014
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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