MB86941 Datasheet, PDF (9/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
2. INTERRUPT REQUESTS (15)
Pin symbol I/O Pin no.
Pin name
IRQ1
I
23 Interrupt Request 1
IRQ2
I
22 Interrupt Request 2
IRQ3
I
15 Interrupt Request 3
IRQ4
I
14 Interrupt Request 4
IRQ5
I
13 Interrupt Request 5
IRQ6
I
12 Interrupt Request 6
IRQ7
I
6 Interrupt Request 7
IRQ8
I
5 Interrupt Request 8
IRQ9
I
4 Interrupt Request 9
IRQ10
I
3 Interrupt Request 10
IRQ11
I
2 Interrupt Request 11
IRQ12
I 144 Interrupt Request 12
IRQ13
I 143 Interrupt Request 13
IRQ14
I 142 Interrupt Request 14
IRQ15
I 141 Interrupt Request 15
Description
Interrupt request pin
Interrupt receiving priority: IRQ15 is highest priority
and IRQ1 is lowest.
A choice of four interrupt waveforms is available by
mode setting for each of the 15 pins independently,
including “H” level, “L” level, rising edge, and falling
edge.
Each input has a filtering function for short pulse
signals, by which an interrupt request is recognized
once a signal is detected at active level at three
successive rising edges of the internal clock signal.
Once an interrupt request is detected, it passes
through priority control and masking control and is
output at the IRL<3:0> pins as an interrupt request to
the MPU.
If these pins are not used, they should be fixed at
inactive level.
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