MB86941 Datasheet, PDF (5/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
s DESCRIPTION OF BLOCK FUNCTIONS
1. BIU (Bus Interface Unit)
This block receives MPU (SPARClite) bus signals and bus controls signals (CLOCK, AS#, RD/WR#, CS#, ADR6
to ADR2, D<15:0>) and generates control signals for accessing MB86941/MB86942 internal resources. It also
returns that Ready signal to the MPU which corresponds to the access time of each of such resources.
2. IRC (Interrupt Request Controller)
This block provides 15-channel interrupt input signals to transmit the interrupt level IRL <3:0> for each interrupt
to the SPARClite.
3. TM (Timer) and PRS (Prescaler)
TM0 to TM3 are 16-bit timers serving as periodic interrupt generation timers, a watchdog timer, and an external
event counter. The operating clock can be selected from among the internal clock, the clock frequency-divided
by the prescaler, and the external clock.
Prescalers 0 and 1 are linked with timer channels 0 and 1, respectively. Each of the prescalers is initialized upon
loading (or reloading) of the timer initial value of the corresponding timer.
4. SDTR (Serial Data Transmitter Receiver)
SDTR0 and SDTR1 are serial data transmitter/receiver modules programmable for control of transmission and
reception.
The programming model is the same as that for the MB89251A.
5. RCSTG (Read/Write Timing Generator)
This module generates read, write, and data strobe signals conforming to the required timings for external
connection of other devices. The assert timing and pulse width of each signal to be generated is programmable.
6. IP (I/O Port)
There are 16 I/O ports. The input/output direction of each port can be set by the control register.
7. SIO (Serial Data Input Output)
This block is a clock-synchronous serial interface. The transfer clock signal can be set to the internally generated
or externally input one. The SIO outputs data to be transmitted and inputs received data in synchronization with
the transfer clock signal.
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