MB86941 Datasheet, PDF (29/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
• Timer output 2
Parameter
OUT output delay time*
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Value
Symbol
Unit
Min.
Max.
tOUTD2
—
3 tCLK + 30
ns
tCLK: See “(2) Clock Signals”.
* : Applied to the following cases.
• Setting mode (write to TCR).
• After setting to MODE0, write to RELOAD register/read COUNT register.
• After setting to MODE1, write to RELOAD register/read COUNT register.
• After setting to MODE3, write to RELOAD register.
CLOCK
AS#
CS#
RD/WR#
Set to MODE, read count
RS < 5 : 0 >
READY1#
READY2#*
High-Z
MB86942: “H” level output
OUTx
* : Only for MB86941.
High-Z
MB86942: “H” level output
tOUTD2
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