MB86941 Datasheet, PDF (30/49 Pages) Fujitsu Component Limited. – Peripheral LSI for SPARClite

MB86941/942
(6) SDTR
• DSR#, RRDY
Parameter
DSR# setup time for resistor read
Interval from register read to RRDY off
tCLK: See “(2) Clock Signals”.
(MB86941: VDD = 5 V ± 5%, TA = 0 to +70°C)
(MB86942: VDD = 3.3 V ± 0.15 V, TA = 0 to +70°C)
Value
Symbol
Unit
Min.
Max.
tDSRS
28
—
tCLK
tRRDYL
0
100
ns
CLOCK
AS#
CS#
RS < 5 : 0 >
RD/WR#
Register read
D < 15 : 0 >
READY1#
READY2#*
DSR#
High-Z
MB86942: “H” level output
tDSRS
RRDY
* : Only for MB86941.
tRRDYL
30
High-Z
MB86942: “H” level output